Multi-test method for using compare MISR
US7631237B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 2005 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit. Test bit patterns are scanned into the scan chains, propagated through the functional logic, and captured in scan chains following the functional logic. The bits are scanned out of the scan chains into a self-compare MISR that creates a signature from the computed bit patterns and then compares the signature of the computed bit patterns with an expected signature, giving a pass/fail result. This single bit result reduces the bandwidth required to communicate the result(s) of the LBIST testing to the test equipment. As a result, a larger number of devices can be tested by a given piece of test equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.