Semiconductor chip with a porous single crystal layer and manufacturing method of the same
US7632696B2 · kind B2 · utility
0Cited by
2References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.