Method of manufacturing wafer level package
US7632709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2008 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Jun 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1517
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.