Arrangement for solder bump formation on wafers
US7632750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2006 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Aug 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.