Memory cell
US7633110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2004 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Jun 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.