Semiconductor package having plural chips side by side arranged on a leadframe
US7633143B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2008 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Sep 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with multiple chips side-by-side disposed on a leadframe is revealed, primarily comprising a plurality of leads of a leadframe, a first chip, a second chip, and an encapsulant to encapsulate the chips where the chip thickness of the second chip is larger than the one of the first chip. The first chip and the second chip are individually disposed on a first die-attaching area and on a second die-attaching area of the leads or a die pad of the leadframe. The second die-attaching area is downset relative to the first die-attaching area in a manner that a bottom surface of the encapsulant is closer to the second die-attaching areas than to the first die-attaching areas. Therefore, when chips with different thicknesses are side-by-side disposed, there is no unbalanced mold flow nor package warpage issue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.