Parallel pipeline graphics system
US7633506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Nov 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.