Integrated circuit support structures and their fabrication
US7635641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Apr 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0733
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.