In-line reliability test using E-beam scan
US7635843B1 · kind B1 · utility
73Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of testing a semiconductor wafer having a test structure performs an E-beam stress scan of the test structure in an E-beam system to electrically stress the test structure to produce a stress defect. An inspection scan is performed in the E-beam system to identify the stress defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.