Integrated circuits, memory controller, and memory modules
US7636258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2007 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Dec 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.