Vertical-channel junction field-effect transistors having buried gates and methods of making
US7638379B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Nov 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.