Microelectronic package having solder-filled through-vias
US7638867B2 · kind B2 · utility
1Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Sep 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method, and a system associated with microelectronic packaging are disclosed herein. In various embodiments, a microelectronic package may include a die having one or more through-vias, each filled with a solder material; a substrate; and one or more solder bumps disposed between and electrically connecting the substrate and a backside of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.