Patent · US Active

Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

US7639046B2 · kind B2 · utility

1Cited by

0References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Gemmeke · Santa Clara, US
Jens Leenstra · Nagold, DE
Jochen Preiss · Eppelheim, DE

Key dates

Filing date	Sep 6, 2007
Grant date	Dec 29, 2009
Priority date	—
Expiry date	Dec 19, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0016
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.