Circuit and method for suppressing gate induced drain leakage
US7639066B2 · kind B2 · utility
11Cited by
8References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jul 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.