Configurable random-access-memory circuitry
US7639557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.