Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications
US7640155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2005 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.