Manufacturing method for partially-good memory modules with defect table in EEPROM
US7642105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Aug 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.