Manufacturing method of chip package
US7642137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Oct 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8582
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.