Methods for removing sidewall spacers
US7642147B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Oct 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for removing sidewall spacers. The method includes: (a) forming a gate stack on a substrate; after (a), (b) forming dielectric spacers on sidewalls of the gate stack; after (b), (c) forming a dielectric sacrificial layer over the substrate and on the gate stack where the substrate and the gate stack are not covered by the spacers; and after (c), (d) removing the sacrificial layer and the spacers in a etch process by etching the sacrificial layer until the spacers are exposed and thereafter simultaneously etching the sacrificial layer and the spacers until the sacrificial layer and the spacers are removed. Methods for spacer removal from PFETs when a stress layer is formed over the NFETs are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.