Inventor · Niskayuna, NY, US

Sivananda K. Kanakasabapathy

204Patents
16h-index
148Co-inventors
89Inventor score

Filing activity: Mar 28, 2001 → Oct 5, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8637384B2 FinFET parasitic capacitance reduction using air gap Electricity 355 Active
US8637930B2 FinFET parasitic capacitance reduction using air gap Electricity 83 Active
US8298943B1 Self aligning via patterning Electricity 53 Active
US9287135B1 Sidewall image transfer process for fin patterning Electricity 44 Active
US8358012B2 Metal semiconductor alloy structure for low contact resistance Electricity 37 Active
US9589845B1 Fin cut enabling single diffusion breaks Electricity 34 Active
US8420464B2 Spacer as hard mask scheme for in-situ doping in CMOS finFETs Electricity 28 Active
US7112861B2 Magnetic tunnel junction cap structure and method for forming the same Electricity 25 Expired
US9209178B2 finFET isolation by selective cyclic etch Emerging Cross-Sectional Technologies 24 Active
US8455364B2 Sidewall image transfer using the lithographic stack as the mandrel Electricity 22 Active
US9472506B2 Registration mark formation during sidewall image transfer process Electricity 22 Active
US9543435B1 Asymmetric multi-gate finFET Electricity 19 Active
US9431399B1 Method for forming merged contact for semiconductor device Electricity 18 Active
US9721848B1 Cutting fins and gates in CMOS devices Electricity 17 Active
US7642147B1 Methods for removing sidewall spacers Electricity 17 Active
US9741823B1 Fin cut during replacement gate formation Electricity 16 Active
US7825000B2 Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions Emerging Cross-Sectional Technologies 16 Active
US7531367B2 Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit Electricity 16 Active
US9991156B2 Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs Electricity 14 Active
US8586478B2 Method of making a semiconductor device Electricity 14 Active
US9754798B1 Hybridization fin reveal for uniform fin reveal depth across different fin pitches Electricity 13 Active
US9305845B2 Self-aligned quadruple patterning process Emerging Cross-Sectional Technologies 13 Active
US8735296B2 Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer Electricity 13 Active
US9064813B2 Trench patterning with block first sidewall image transfer Electricity 13 Active
US8518824B2 Self aligning via patterning Electricity 13 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.