Methods for forming gate electrodes for integrated circuits
US7642153B2 · kind B2 · utility
9Cited by
14References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.