Semiconductor memory device and method of production

US7642158B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stefano Parascandola · Dresden, DE
• Roman Knoefler · Villach, AT
• Stephan Riedel · Frankfurt am Main, DE
• Dominik Olligs · Dresden, DE
• Torsten Mueller · Zirndorf, DE
• Dirk Caspary · Dresden, DE

Key dates

• Filing date: Sep 30, 2005
• Grant date: Jan 5, 2010
• Expiry date: Oct 6, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.