Patent · US Active

Integrated circuit having a memory cell array and method of forming an integrated circuit

US7642572B2 · kind B2 · utility

16Cited by

8References

20Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Martin Popp · Dresden, DE
Till Schloesser · Dresden, DE
Ulrike Gruening-von Schwerin · Birkenfeld, DE
Rolf Weis · Dresden, DE

Key dates

Filing date	Apr 13, 2007
Grant date	Jan 5, 2010
Priority date	—
Expiry date	Apr 13, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH10B12/482
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.