Semiconductor architecture having field-effect transistors especially suitable for analog applications

US7642574B2 · kind B2 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventor

• Constantin Bulucea · Milpitas, US

Key dates

• Filing date: Oct 31, 2007
• Grant date: Jan 5, 2010
• Expiry date: Oct 31, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.