Semiconductor device and fabrication method of same
US7642604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Feb 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.