Method for synchronizing a clock signal with a reference signal, and phase locked loop
US7642821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period. The method includes generating a phase difference signal which is proportional to a phase difference between the clock signal and the reference signal, filtering the phase difference signal and providing a filtered phase difference signal, driving a digital oscillator in such a manner that the frequency of the clock signal is changed on the basis of the filtered phase difference signal, the phase of the clock signal within a clock period being corrected by a value corresponding to the fraction of the clock period at an end of the pause in the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.