Asymmetric four-transistor SRAM cell
US7643329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.