Integrated circuit having a memory arrangement

US7643341B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Christoph Deml · Munich, DE
• Thomas Liebermann · Munich, DE
• Edvin Paparisto · Munich, DE

Key dates

• Filing date: Feb 28, 2007
• Grant date: Jan 5, 2010
• Expiry date: Jan 31, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.