System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture
US7643357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Apr 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.