Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

US7643591B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Igor Arsovski · Williston, US
• Serafino Bueti · Waterbury, US
• Joseph A. Iadanza · South Burlington, US
• Jason M. Norman · South Burlington, US
• Hemen R. Shah · South Burlington, US
• Sebastian T. Ventrone · South Burlington, US

Key dates

• Filing date: Jul 26, 2006
• Grant date: Jan 5, 2010
• Expiry date: Jan 23, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/02
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.