Igor Arsovski
108Patents
11h-index
86Co-inventors
79Inventor score
Filing activity: Nov 7, 2003 → May 30, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8363453B2 | Static random access memory (SRAM) write assist circuit with leakage suppression and level control | Physics | 37 | Active |
| US8117567B2 | Structure for implementing memory array device with built in computation capability | Physics | 33 | Active |
| US7646648B2 | Apparatus and method for implementing memory array device with built in computational capability | Physics | 32 | Active |
| US9177646B2 | Implementing computational memory from content-addressable memory | Physics | 26 | Active |
| US7830727B2 | Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines | Physics | 20 | Active |
| US7924588B2 | Content addressable memory with concurrent two-dimensional search capability in both row and column directions | Physics | 18 | Active |
| US7006368B2 | Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories | Physics | 17 | Expired |
| US8793365B2 | Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes | Emerging Cross-Sectional Technologies | 16 | Active |
| US7483806B1 | Design structures, method and systems of powering on integrated circuit | Emerging Cross-Sectional Technologies | 15 | Active |
| US8077534B2 | Adaptive noise suppression using a noise look-up table | Physics | 14 | Active |
| US8233337B2 | SRAM delay circuit that tracks bitcell characteristics | Physics | 13 | Active |
| US8233302B2 | Content addressable memory with concurrent read and search/compare operations at the same memory cell | Physics | 11 | Active |
| US8525546B1 | Majority dominant power scheme for repeated structures and structures thereof | Physics | 10 | Active |
| US7986571B2 | Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines | Physics | 10 | Active |
| US7643591B2 | Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design | Electricity | 9 | Active |
| US7688611B2 | CAM asynchronous search-line switching | Physics | 8 | Active |
| US7751218B2 | Self-referenced match-line sense amplifier for content addressable memories | Physics | 8 | Active |
| US9172371B2 | Majority dominant power scheme for repeated structures and structures thereof | Physics | 8 | Active |
| US7940581B2 | Method for low power sensing in a multi-port SRAM using pre-discharged bit lines | Physics | 8 | Active |
| US9224091B2 | Learning artificial neural network using ternary content addressable memory (TCAM) | Physics | 8 | Active |
| US8130525B2 | Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM | Physics | 7 | Active |
| US8214699B2 | Circuit structure and method for digital integrated circuit performance screening | Physics | 6 | Active |
| US7362138B1 | Flexible multimode logic element for use in a configurable mixed-logic signal distribution path | Electricity | 6 | Active |
| US7429877B2 | Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path | Electricity | 6 | Active |
| US7823107B2 | Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.