Programmable logic device integrated circuits with configurable dynamic phase alignment circuitry
US7644296B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Programmable logic device integrated circuits are provided that have configurable receivers with dynamic phase alignment capabilities. In situations in which receivers require dynamic phase alignment circuitry, programmable logic elements can be configured to implement a dynamic phase alignment data capture and synchronization circuit. In situations in which dynamic phase alignment receiver circuitry is not required, resources are made available for implementing other user logic. Multiple dynamic phase alignment receiver circuits can share an eight-phase dynamic phase alignment clock signal that is generated by a phase-locked-loop circuit. Switches may be configured to selectively route the dynamic phase alignment clock signal to desired locations on the programmable logic device integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.