Data line layout in semiconductor memory device and method of forming the same
US7645644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2008 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n<m, and M=m+1, and a first decoder region and a second decoder region respectively located on opposite sides of the data block. A first data line group among the M data lines extend to the first decoder region from the data block, and a second data line group among the M data lines extend to the second decoder region from the data block. The first data line group includes even numbered data lines among the data lines {0, 1, 2, . . . n}, and odd numbered data lines among the data lines {n+1, . . . m−1, m}, and the second data line group includes odd numbered data lines among the data lines {0, 1, 2, . . . n}, and even numbered data lines among the data lines {n+1, . . . m−1, m}.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.