Double gated transistor and method of fabrication

US7645650B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Andres Bryant · South Burlington, US
• Meikei Ieong · Wappingers Falls, US
• K. Paul Muller · Wappingers Falls, US
• Edward J. Nowak · South Burlington, US
• David M. Fried · Ithaca, US
• Jed H. Rankin · South Burlington, US

Key dates

• Filing date: Jul 9, 2007
• Grant date: Jan 12, 2010
• Expiry date: Dec 15, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.