JFET with built in back gate in either SOI or bulk silicon
US7645654B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2008 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.