Layout pattern for deep well region to facilitate routing body-bias voltage
US7645664B1 · kind B1 · utility
1Cited by
28References
24Claims
0Family size
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.