Phase locked loop circuit having set initial locking level and control method thereof
US7646223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Sep 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.