Patent · US Active

Integrated circuit for setting a memory cell based on a reset current distribution

US7646632B2 · kind B2 · utility

14Cited by

7References

23Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Jan Boris Philipp · Peekskill, US
Thomas Happ · Tarrytown, US
Bernhard Ruf · Sauerlach, DE
Christian Ruster · Augsburg, DE
Dieter Andres · Munich, DE
Petra Majewski · Munich, DE

Key dates

Filing date	Dec 21, 2007
Grant date	Jan 12, 2010
Priority date	—
Expiry date	Jul 24, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.