Apparatus and method for implementing memory array device with built in computational capability
US7646648B2 · kind B2 · utility
32Cited by
12References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.