Semiconductor memory device and burn-in test method thereof
US7646665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Jul 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.