System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation
US7647539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2007 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Feb 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.