Inventor · Bengaluru, IN

Manoj Dusanapudi

67Patents
8h-index
40Co-inventors
74Inventor score

Filing activity: Jul 18, 2007 → Feb 23, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7647539B2 System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Physics 23 Active
US7752499B2 System and method for using resource pools and instruction pools for processor design verification and validation Physics 19 Active
US7669083B2 System and method for re-shuffling test case instruction orders for processor design verification and validation Physics 16 Active
US7992059B2 System and method for testing a large memory area during processor design verification and validation Physics 13 Active
US9612929B1 Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems Physics 12 Active
US7797650B2 System and method for testing SLB and TLB cells during processor design verification and validation Physics 11 Active
US9910941B2 Test case generation Physics 11 Active
US7747908B2 System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation Physics 10 Active
US8832502B2 Hardware verification using acceleration platform Physics 8 Active
US7661023B2 System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation Physics 7 Active
US9594680B1 Identifying stale entries in address translation cache Physics 6 Active
US9514036B1 Test case generation Physics 5 Active
US9501408B2 Efficient validation of coherency between processor cores and accelerators in computer systems Physics 4 Active
US7584394B2 System and method for pseudo-random test pattern memory allocation for processor design verification and validation Physics 4 Active
US7689886B2 System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation Physics 4 Active
US8127192B2 Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode Physics 4 Active
US7739570B2 System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation Physics 4 Active
US8099559B2 System and method for generating fast instruction and data interrupts for processor design verification and validation Physics 4 Active
US10169186B1 Efficient testing of direct memory address translation Physics 3 Active
US9542290B1 Replicating test case data into a cache with non-naturally aligned data boundaries Physics 3 Active
US7966521B2 Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics Physics 3 Active
US9043569B2 Memory data management Physics 2 Active
US9298516B2 Verification of dynamic logical partitioning Physics 2 Active
US9286133B2 Verification of dynamic logical partitioning Physics 2 Active
US10169185B1 Efficient testing of direct memory address translation Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.