Method and device for testing delay paths of an integrated circuit
US7647573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | May 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay measurements for the critical delay paths. The critical delay paths are ranked based on the actual delay measurements, and the results are correlated to the predicted ranking of critical delay paths to produce a confidence measurement that measures the likelihood that the actual critical delay paths of the design have been tested for a given production batch of devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.