Semiconductor device, stacked structure, and manufacturing method
US7649249B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jan 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to the other major surface. The semiconductor device can be manufactured from a semiconductor wafer by creating holes that penetrate partway through the wafer, filling the holes with metal to form the electrically conductive members and thermally conductive members, and then grinding the lower surface of the wafer to expose the ends of the electrically conductive members and thermally conductive members before dicing the wafer into chips. The thermally conductive members improve heat dissipation performance when semiconductor chips of this type are combined into a stacked multichip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.