Method, apparatus, and system for increasing single core performance in a multi-core microprocessor
US7650518B2 · kind B2 · utility
28Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jan 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.