Programmable interconnect for reconfigurable system-on-chip
US7650545B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2003 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318519
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Signals sent from one system-on-chip core become switched to a reconfigurable logic core (RLC) for observation and, perhaps, replacement with another signal. A first signal line couples together a plurality of cores. A switch, disposed between the first signal line and an input signal line of the RLC, selectively controls whether the signal gets sent to the RLC. A multiplexer, having the first signal line and an output signal line of the RLC as inputs, selectively controls whether the signal or a replacement signal becomes conveyed to another core of the system-on-chip. Observation and control configuration memory bits act as inputs in the selective control of the switch and the multiplexer. Other embodiments teach shared RLC input signal lines amongst multiple cores. The RLC may contain an inverter, a test circuit, a logic analyzer or other. Methods of observing and replacing signals are also taught.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.