Method and an integrated circuit for performing a test

US7650554B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gottfried Goldrian · Eppelheim, DE
• Otto A. Torreiter · Echterdingen, DE
• Dieter Wendel · Schenefeld, DE

Key dates

• Filing date: Nov 28, 2006
• Grant date: Jan 19, 2010
• Expiry date: Oct 4, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31922
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.