Otto A. Torreiter
40Patents
5h-index
41Co-inventors
69Inventor score
Filing activity: Oct 23, 1992 → Sep 29, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5742616A | System and method testing computer memories | Physics | 50 | Expired |
| US5485473A | Method and system for testing an integrated circuit featuring scan design | Physics | 19 | Expired |
| US6127254A | Method and device for precise alignment of semiconductor chips on a substrate | Electricity | 17 | Expired |
| US5369358A | Method of ensuring electrical contact between test probes and chip pads through the use of vibration and nondestructive deformation | Physics | 8 | Expired |
| US6774656B2 | Self-test for leakage current of driver/receiver stages | Physics | 6 | Expired |
| US6725171B2 | Self-test with split, asymmetric controlled driver output stage | Physics | 5 | Expired |
| US7650554B2 | Method and an integrated circuit for performing a test | Physics | 5 | Active |
| US9217758B2 | Ball grid array configuration for reliable testing | Physics | 5 | Active |
| US8535956B2 | Chip attach frame | Emerging Cross-Sectional Technologies | 4 | Active |
| US9977053B2 | Wafer probe alignment | Physics | 4 | Active |
| US9740813B1 | Layout effect characterization for integrated circuits | Physics | 4 | Active |
| US7636254B2 | Wordline booster circuit and method of operating a wordline booster circuit | Physics | 4 | Active |
| US8010934B2 | Method and system for testing bit failures in array elements of an electronic circuit | Physics | 2 | Active |
| US9401222B1 | Determining categories for memory fail conditions | Physics | 2 | Active |
| US8659310B2 | Method and system for performing self-tests in an electronic system | Physics | 2 | Active |
| US9496188B2 | Soldering three dimensional integrated circuits | Electricity | 2 | Active |
| US7921388B2 | Wordline booster design structure and method of operating a wordine booster circuit | Physics | 2 | Active |
| US9322848B2 | Ball grid array configuration for reliable testing | Physics | 2 | Active |
| US9927463B2 | Wafer probe alignment | Physics | 2 | Active |
| US8866504B2 | Determining local voltage in an electronic system | Physics | 1 | Active |
| US11262381B2 | Device for positioning a semiconductor die in a wafer prober | Physics | 1 | Active |
| US9709625B2 | Measuring power consumption in an integrated circuit | Physics | 1 | Active |
| US10114914B2 | Layout effect characterization for integrated circuits | Physics | 0 | Active |
| US10056346B2 | Chip attach frame | Emerging Cross-Sectional Technologies | 0 | Active |
| US11209479B2 | Stressing integrated circuits using a radiation source | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.