Metal interconnect structure and method
US7651942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2005 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.