Buffer circuit, amplifier circuit, and test apparatus
US7652466B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2007 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Apr 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5021
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided a buffer circuit that outputs a signal according to an input signal. The buffer circuit includes a first receiving transistor that receives the input signal through its base terminal, a first clamp transistor having polarity same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal, and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor. The buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.